1. Field of the Invention
Embodiments of the invention relate to semiconductor devices and semiconductor device manufacturing methods.
2. Related Art
Although power diodes are utilized in various applications, in recent years they are being used in high frequency circuits for power, and the like, and there is a strong demand for high speed, low loss (low Vf (forward voltage drop)), and low Err (reverse recovery loss). Furthermore, there is a strong demand for soft recovery characteristics with an object of, as well as obtaining high speed and low loss, suppressing radiation noise. Hereafter, a description will be given of a p-i-n (p-intrinsic-n) diode structuring method.
FIGS. 9(a)-9(f) are sectional views showing conditions partway through the manufacture of a heretofore known semiconductor device. Firstly, there is prepared a low resistivity (approximately 20 mΩcm) n-type semiconductor substrate (an antimony-doped substrate) with a thickness of 625 doped with antimony (Sb). This n-type semiconductor substrate is an n-type cathode layer 51. Next, there is fabricated a wafer wherein an n-type epitaxial layer 100 with a thickness of 60 μm and a resistivity of 20 Ωcm is formed by being epitaxially grown on the semiconductor substrate while doping with phosphorus (P) (FIG. 9(a)).
Next, an implantation of boron (B) ions into the front surface (the surface on the n-type epitaxial layer 100 side) of the wafer is carried out to a dose of 7.0×1013/cm2, after which heat treatment is carried out at a temperature of 1,150° C., by doing which a p-type anode layer 53 is selectively formed in a surface layer of the n-type epitaxial layer 100 (FIG. 9(b). The n-type epitaxial layer 100 sandwiched between the p-type anode layer 53 and n-type cathode layer 51 becomes an n− type drift layer 52.
Next, a grinding and etching 68 of the back surface (the surface on the n-type cathode layer 51 side) is carried out until the total thickness of the wafer is, for example, 300 μm (FIG. 9(c)). Next, after an ion implantation 69 of arsenic (As) is carried into the back surface of the wafer on which the grinding and etching 68 has been carried out in order to ensure good ohmic contact, heat treatment is carried out at a temperature of 1,000° C. or more, thus forming an n-type contact layer 54 in the ground back surface of the wafer (FIG. 9(d)).
Next, an anode electrode 55 is formed of aluminum (Al) or the like on the wafer front surface (FIG. 9(e)). Subsequently, a cathode electrode 56 is deposited by vapor deposition, or the like, on the wafer back surface (FIG. 9(f)), thereby completing the heretofore known p-i-n diode. Reference sign 57 in the drawing is an interlayer dielectric that isolates the anode electrode 55 and n-type epitaxial layer 100 with an edge termination structure region. This kind of heretofore known diode structure and manufacturing method are proposed in, for example, Japanese Patent Application Publication No. JP-A-2004-39842.
Also, as a method of realizing ohmic contact between a semiconductor substrate (wafer) and metal electrode, there has been proposed a method whereby, after the thickness of the semiconductor substrate is reduced by etching or the like, an impurity of the same conductivity as the semiconductor substrate is ion implanted, and a high concentration layer formed in the semiconductor substrate surface by activating the impurity by heat treatment at in the region of 800° C., thus obtaining good ohmic contact. See, for example, Japanese Patent Application Publication No. JP-A-49-22080 (also referred to herein “PTL 2”).
Also, as another method, there has been proposed a method whereby a low temperature heat treatment is carried out in order to avoid an adverse effect of a high temperature heat treatment on a semiconductor substrate front surface side device structure. See, for example, Japanese Patent Application Publication No. JP-A-4-214671 (also referred to herein as “PTL 3”). In PTL 3, after an ion implantation is carried out into the semiconductor substrate back surface, a titanium (Ti) layer, of a plurality of metal layers stacked as a back surface electrode, is deposited first, and the remainder of the metal layers that form the back surface electrode are deposited after a heat treatment is carried out at a low temperature of 400° C. or less for a short time of 30 minutes or less. It is disclosed that at this time, in the case of an n-type silicon substrate, the impurity ion-implanted into the substrate back surface is arsenic (As).
Also, as another method, there is proposed a method whereby an n-type impurity with which a low resistivity n-type semiconductor substrate is doped is arsenic. See, for example, Japanese Patent Application Publication No. JP-A-2000-58867 (also referred to herein as “PTL 4”). By adopting an arsenic-doped n-type semiconductor substrate (an arsenic-doped substrate), as in PTL 4, it is possible for the n-type impurity concentration of the n-type semiconductor substrate to be 1.0×1019/cm3 or more. This is because the solid solubility of arsenic is higher than the solid solubility of antimony. As the impurity concentration of the arsenic-doped substrate is high enough that ohmic contact with a metal electrode is possible in this way, it is possible to form a back surface electrode on the substrate itself, without forming a high concentration impurity layer using an ion implantation, or the like.
In recent years, there has been a strong demand for high reliability, meaning an improvement in heat cycle tolerance, in power devices, and there is a demand for chips to be thinner than to date in order to realize high reliability. Furthermore, along with a reduction in wafer thickness in order for chips to be thinner than to date, there has been an increase in wafer size in order to reduce cost, because of which there is a large problem of reducing the rate of crack defects caused by the reduction in wafer thickness. In order to suppress cracking of wafers reduced in thickness without large equipment investment, the degree to which the number of processing steps after reducing the wafer thickness can be reduced is important.
The heretofore known p-i-n diode manufacturing method shown in FIG. 9 is such that the thickness is reduced by grinding the wafer back surface and, after arsenic is ion implanted into the ground back surface of the wafer and a high temperature heat treatment is carried out, the front surface element structure, including the front surface electrode, and the back surface electrode are formed. This method is such that, as the step of forming the front surface element structure and the step of forming the back surface electrode are carried out with the wafer in a thin state, it is difficult to handle (convey) the wafer so as to avoid cracking of the wafer, scratching of the front surface and back surface, and the like, and there is a problem in that the yield rate decreases. Also, when forming the n-type contact layer 54 on the wafer back surface, it is necessary to carry out the heat treatment after the arsenic ion implantation at a temperature of in the region of 1,000° C., and wafer warpage is liable to occur. Flatness of the wafer front surface is lost due to the warpage, and there is a problem in that patterning of the front surface electrode formation, and the like, in a subsequent step is difficult.
Also, as previously described, problems with an antimony-doped substrate are that the solid solubility is low, the resistivity is high compared with the resistivity of an arsenic-doped substrate, contact resistance with the cathode electrode increases because of the high resistivity, and there is an increase in variation of contact resistance with the cathode electrode. A method whereby, after the thickness of the semiconductor substrate is reduced, an impurity (phosphorus) introduced into the wafer back surface by a high concentration ion implantation is subjected to a heat treatment at a high temperature of 800° C. or more, thereby forming a high concentration layer in order to obtain ohmic contact, as in PTL 2, is feasible as a method of eliminating these problems.
However, the kind of method in PTL 2 is such that, as the melting point of aluminum, which is commonly used as the front surface electrode, is in the region of 660° C., a large number of steps, such as an aluminum film formation and a photo etching, are carried out with the wafer in a state of reduced thickness. As a result of this, the frequency of mechanical stress exerted by a wafer chuck, or the like, increases, and a new problem occurs in that the probability of the wafer cracking becomes extremely high.
Meanwhile, when a high concentration of phosphorus is ion implanted into a semiconductor substrate, a large number of defects remain in the implantation surface and, depending on the implantation dose, it may happen that the ion implantation layer becomes amorphous. However, when the heat treatment temperature is lower than 800° C., as in PTL 3, the crystallization of the ion implantation layer does not recover, and a large number of defects remain. When a large number of defects remain and crystallization does not recover in this way, the introduced impurity is not electrically activated. Because of this, the resistance of the contact with the electrode increases, and there is a problem in that the forward voltage drop of the diode increases.
When using an arsenic-doped substrate rather than an antimony-doped substrate, as in PTL 4, there is no need to form a high concentration impurity layer on the cathode side and, after all of the front surface element structure, such as the front surface electrode formation, is formed, it is possible to form the cathode electrode immediately after the thickness of the wafer is reduced. Consequently, the only step carried out on the wafer reduced in thickness is the step of forming the back surface electrode, which is advantageous in preventing cracking of the wafer. However, there is a problem in that an arsenic-doped substrate is generally more expensive than an antimony-doped substrate. Furthermore, a wafer wherein an n-type epitaxial layer is formed on an arsenic-doped substrate is such that the in-plane resistance value of the wafer is liable to vary due to auto-doping from the arsenic-doped substrate during epitaxial growth, and there is a problem in that the device characteristics vary.